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| RF12B V1.1 RF12B Universal ISM Band FSK Transceiver DESCRIPTION Hope's multi-channel RF12B FSK is a single chip, low for power, use in transceiver designed RF12B applications requiring FCC or ETSI conformance for unlicensed use in the 433, 868 and 915 MHz bands. The RF12B transceiver produces a flexible, low cost, and highly integrated solution that does not require production alignments. The chip is a complete analog RF and baseband transceiver including a multi-band PLL synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. The RF12B features a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multi-path fading and interference to achieve robust wireless links. The PLL's high resolution allows the usage of multiple channels in any of the bands. The receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation. Consequently, no external components (except crystal and decoupling) are needed in most applications. The RF12B dramatically reduces the load on the microcontroller with the integrated digital data processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost) crystal. To minimize the system cost, the RF12B can provide a clock signal for the microcontroller, avoiding the need for two crystals. For low power applications, the RF12B supports low duty cycle operation based on the internal wake-up timer. FUNCTIONAL BLOCK DIAGRAM Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 FEATURES Fully integrated (low BOM, easy design-in) No alignment required in production Fast-settling, programmable, high-resolution PLL synthesizer Fast frequency-hopping capability High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode) Direct differential antenna input/output Integrated power amplifier Programmable TX frequency deviation (15 to 240 kHz) Programmable RX baseband bandwidth (67 to 400 kHz) Analog and digital RSSI outputs Automatic frequency control (AFC) Data quality detection (DQD) Internal data filtering and clock recovery RX synchron pattern recognition SPI compatible serial control interface Clock and reset signals for microcontroller 16 bit RX Data FIFO Two 8 bit TX data registers Low power duty cycle mode Standard 10 MHz crystal reference Wake-up timer 2.2 to 3.8 V supply voltage Low power consumption Low standby current (0.3 A) Supports very short packets (down to 3 bytes) Excellent temperature stability of the RF parameters TYPICAL APPLICATIONS Remote control Home security and alarm Wireless keyboard/mouse and other PC peripherals Toy controls Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 DETAILED FEATURE-LEVEL DESCRIPTION The RF12B FSK transceiver is designed to cover the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The RF12B incorporates a fully integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switch-able gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL's high resolution allows the usage of multiple channels in any of the bands. RF Power Amplifier (PA) The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called "hand effect". LNA The LNA has approximately 250 Ohm input impedance, which functions well with the proposed antennas. If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. The LNA gain can be selected in four steps (between 0 and -20dB relative to the highest gain) according to RF signal strength. It can be useful in an environment with strong interferers. Baseband Filters The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. An chosen appropriate to bandwidth can be FSK accommodate various deviation, data rate and crystal tolerance requirements. The filter structure is 7th order Butterworth low-pass with 40 dB suppression at 2*BW frequency. Offset cancellation is done by using a high-pass filter with a cut-off frequency below 7 kHz. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Data Filtering and Clock Recovery Output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO can not be used in this mode and clock is not provided for the demodulated data. Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode. The CR starts in fast mode, then after locking it automatically switches to slow mode. (Only the digital data filter and the clock recovery use the bit rate clock. For analog operation, there is no need for setting the correct bit rate.) Data Validity Blocks RSSI A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital RSSI can be monitored by reading the status register. Analog RSSI Voltage vs. RF Input Power P1 P2 P3 P4 DQD -65 dBm -65 dBm -100 dBm -100 dBm 1300 mV 1000 mV 600 mV 300 mV The operation of the Data Quality Detector is based on counting the spikes on the unfiltered received data. High output signal indicates an operating FSK transmitter within baseband filter bandwidth from the local oscillator. DQD threshold parameter can be set by using the Data Filter Command. AFC By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the TX/RX offset in discrete steps, allowing the use of: Narrower receiver bandwidth (i.e. increased sensitivity) Higher data rate Inexpensive crystals Crystal Oscillator Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 The RF12B has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transceiver can supply a clock signal for the microcontroller; so accurate timing is possible without the need for a second crystal. When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses ("clock tail") for the microcontroller to let it go to idle or sleep mode. If this clock output is not used, turn the output buffer off by the Power Management Command. Low Battery Voltage Detector The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. The detector circuit has 50mV hysteresis. Wake-Up Timer The wake-up timer has very low current consumption (1.5 A typical) and can be programmed from 1 ms to several days with an accuracy of 5%. It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing even in case of changing ambient temperature and supply voltage. Event Handling In order to minimize current consumption, the transceiver supports different power saving modes. Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the serial interface). If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The source of the interrupt can be read out from the transceiver by the microcontroller through the SDO pin. Interface and Controller An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transceiver and the received data. The transmitter block is equipped with two 8 bit wide TX data registers. It is possible to write 8 bits into the register in burst mode and the internal bit rate generator transmits the bits out with the predefined rate. For further details, see the TX Register Buffered Data Transmission section. It is also possible to store the received data bits into a FIFO register and read them out in a buffered mode. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 PACKAGE PIN DEFINITIONS Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Pin 1 2 3 4 5 6 Name SDI SCK nSEL SDO nIRQ FSK DATA Type DI DI DI DO DO DI DO nFFS DI DLCK DO CFIL AIO FFIT 8 9 10 11 12 13 14 15 16 CLK XTL REF nRES VSS RF2 RF1 VDD ARSSI nINT VDI DO DO AIO AIO DIO S AIO AIO S AO DI DO Function Data input of the serial control interface (SPI compatible) Clock input of the serial control interface Chip select input of the serial control interface (active low) Serial data output with bus hold Interrupt request output (active low) Transmit FSK data input (internal pull up resistor 133 k) Received data output (FIFO not used) FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command Received data clock output (Digital filter used, FIFO not used) External data filter capacitor connection (Analog filter used) FIFO interrupt (active high) Number of the bits in the RX FIFO has reached the preprogrammed limit Microcontroller clock output Crystal connection (the other terminal of crystal to VSS) or external reference input External reference input. Use 33 pF series coupling capacitor Open drain reset output with internal pull-up and input buffer (active low) Ground reference voltage RF differential signal input/output RF differential signal input/output Positive supply voltage Analog RSSI output Interrupt input (active low) Valid data indicator output 7 Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 PIN6(FSK/DATA/nFFS) internal structure PIN10(nRES) internal structure Typical Application Typical application with FIFO usage Pin 6 Transmit mode el=0 in Configuration Setting Command Transmit mode el=1 in Configuration Setting Command Receive mode ef=0 in Configuration Setting Command Receive mode ef=1 in Configuration Setting Command nFFS input (RX Data FIFO can be accessed) RX Data output nFFS input (TX Data register can be accessed) TX Data input Pin 7 RX Data clock output FFIT output Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 GENERAL DEVICE SPECIFICATION All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbol Vdd Vin Voc Iin ESD Tst Parameter Positive supply voltage Voltage on any pin (except RF1 and RF2) Voltage on open collector outputs (RF1, RF2) Input current into any pin except VDD and VSS Electrostatic discharge with human body model Storage temperature -55 Min -0.5 -0.5 -0.5 -25 Max 6 Vd d +0.5 Vd d +1.5 (Note 1) 25 1000 125 Units V V V mA V Recommended Operating Range Symbol Vdd VocDC VocAC Top Parameter Positive supply voltage DC voltage on open collector outputs (RF1, RF2) AC peak voltage on open collector outputs (RF1, RF2) Ambient operating temperature Min 2.2 Max 3.8 Units V V V Vd d -1.5 Vd d +1.5 (Note 2) Vd d +1 .5 -40 85 Note 1: Cannot be higher than 7 V. Note 2: Cannot be lower than 1.2 V. ELECTRICAL SPECIFICATION (Min/max values are valid over the whole recommended operating range. Typical conditions: Top= 27; Vdd=Voc=2.7V) DC Characteristics Symbol Idd_TX_0 Parameter Supply current (TX mode, Pout = 0 dBm) Supply current (TX mode, Pout = Pmax ) Supply current (RX mode) Standby current (Sleep mode) Low battery voltage detector current consumption Wake-up timer current consumption Idle current Crystal oscillator on (Note 3) Conditions/Notes 433 MHz band 868 MHz band 915 MHz band 433 MHz band 868 MHz band 915 MHz band 433 MHz band 868 MHz band 915 MHz band All blocks disabled Min Typ 15 16 17 22 23 24 11 12 13 0.3 0.5 1.5 0.62 1.2 Max Units 17 18 19 24 25 26 13 14 15 A A A mA mA mA mA Idd_TX_PMAX Idd_RX Ipd Ilb Iwt Ix Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Vlb Vlba Vil Vih Iil Iih Vol Voh Low battery detect threshold Low battery detection accuracy Digital input low level voltage Digital input high level voltage Digital input current Digital input current Digital output low level Digital output high level Vil = 0 V Vih = Vdd , Vdd = 3.8 V Iol = 2 mA Ioh = -2 mA Vdd -0.4 0.7 Vdd -1 -1 1 1 0.4 * Programmable in 0.1V steps 2.2 3 3.7 V % 0.3 Vdd * V V A A V V AC Characteristics (PLL parameters) Symbol fref fo tlock tst, P Parameter PLL reference frequency Receiver LO/Transmitter carrier frequency PLL lock time PLL startup time Conditions/Notes (Note 1) 433 MHz band, 2.5 kHz resolution 868 MHz band, 5.0 kHz resolution 915 MHz band, 7.5 kHz resolution Frequency error < 1kHz ft 10 MH t With a running crystal oscillator Min 9 430.24 860.48 900.72 Typ 10 Max Units 11 MHz 439.75 879.51 MHz 929.27 us 300 us 30 200 AC Characteristics (Receiver) Symbol Parameter Conditions/Notes mode 0 mode 1 BW Receiver bandwidth mode 2 mode 3 mode 4 mode 5 BRRX FSK bit rate With internal digital filters With analog filter -3 Min 60 120 180 240 300 360 0.6 Typ 67 134 200 270 340 400 Max Units 75 150 225 300 380 450 115.2 kbps 256 kbps kHz BRARX FSK bit rate Pmin Receiver Sensitivity BER 10 , BW=67 kHz, BR=1.2 kbps (Note 2) -109 -103 dBm AFCrange AFC locking range dfFSK: FSK deviation in the received signal IIP3inh Input IP3 IIP3outh Input IP3 IIP3inl IIP3outl Pmax Cin RSa RSr IIP3 (LNA -6 dB gain) IIP3 (LNA -6 dB gain) Maximum input power RF input capacitance RSSI accuracy RSSI range In band interferers in high bands (868, 915 MHz) Out of band interferers 0.8*dfFSK -21 -18 -15 dBm dBm dBm l f-fo l > 4 MHz In band interferers in low band (433 MHz) Out of band interferers l f-fo l > 4 MHz LNA: high gain 0 -12 dBm dBm 1 +/-5 46 pF dB dB Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 CARSSI Filter capacitor for ARSSI RSSI programmable 1 nF 6 Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit CARRSI = 4.7 nF dB RSstep RSresp Psp_rx level steps DRSSI response time Receiver spurious emission 500 us -60 dBm AC Characteristics (Transmitter) Symbol Parameter IOUT Open collector output DC current Max. output power delivered to 50 Conditions/Notes Programmable In 433 MHz band In 868 / 915 MHz bands In 433 MHz band with monopole antenna with matching network (Note 4) In 868 / 915 MHz bands (Note 5) Selectable in 3 dB steps (Note 8) At max power 50 Ohm load (Note 4) With PCB antenna (Note 5) At max power 50 Ohm load (Note 4) With PCB antenna (Note 5) In 433 MHz band In 868 / 915 MHz bands In 433 MHz band In 868 / 915 MHz bands 100 kHz from carrier, in 868 MHz band 1 MHz from carrier, in 868 MHz band Via internal TX data register TX data connected to the FSK input Programmable in 15 kHz steps Min 0.5 Typ Max 6 7 5 7 7 Units mA dBm Pmax_50 Ohm load over a suitable matching network (Note 4) Max. EIRP with suitable selected PCB antenna. (Note 6, 7) Typical output power Pmax_ant dBm Pmax -55 -60 -35 -42 dBm dBc dBc dBc dBc pF Pout Psp Pharm Co Qo Lout BRTX BRATX dffsk Pmax-21 Spurious emission l f-fsp l > 1 MHz Harmonic suppression Output capacitance (set by the automatic antenna tuning circuit) Quality factor of the output capacitance Output phase noise FSK bit rate FSK bit rate FSK frequency deviation 2 2.1 13 8 2.6 2.7 15 10 -80 -103 3.2 3.3 17 12 dBc/Hz 172 256 kbps kbps kHz 15 240 AC Characteristics (Turn-on/Turnaround timings) Symbol tsx Ttx_XTAL_ON Receiver turn-on time Trx_XTAL_ON Ttx_rx_SYNT_ON Trx_tx_SYNT_ON Parameter Crystal oscillator startup time Transmitter turn-on time Conditions/Notes Crystal ESR < 100 Ohm Synthesizer off, crystal oscillator on with 10 MHz step Synthesizer off, crystal oscillator on with 10 MHz step Min Typ MaxUnits 15 250 250 150 150 ms us us us us Transmitter - Receiver turnover time Synthesizer and crystal oscillator on during TX/RX change with 10 MHz step Receiver - Transmitter turnover time Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 AC Characteristics (Others) Symbol Cxl tPOR tPBt Cin, D tr, f Parameter Crystal load capacitance, see crystal selection guide Internal POR timeout Wake-up timer clock period Digital input capacitance Digital output rise/fall time 15 pF pure capacitive load Conditions/Notes Programmable in 0.5 pF steps, tolerance +/- 10% After Vdd has reached 90% of final value (Note 9) Calibrated every 30 seconds Min Typ Max Units 8.5 16 100 0.95 pF ms 1.05 ms 2 10 pF ns AC Characteristics (continued) Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will change accordingly. Note 2: See the BER diagrams in the measurement results section for detailed information. Note 3: Measured with disabled clock output buffer. This current can be decreased by enabling the low power mode of the crystal oscillator. See PLL Setting Command and Power Management Command for details. Note 4: See Reference design with 50 Ohm matching network for details. Note 5: See Reference design with resonant PCB antenna (BIFA) for details. Note 6: Supposing identical antenna with RF12B in RX mode, the outdoor RF link range will be approximately 120 meters indoor and 450 meters outdoor. Note 7: Optimal antenna admittance/impedance: RF12B 433 MHz 868 MHz 915 MHz Note 8: Adjustable in 8 steps. Note 9: During this period, commands are not accepted by the chip. Yantenna [S] 1.4E-3 - j7.1E-3 2E-3 - j1.5E-2 2.2E-3 - j1.55E-2 Zantenna [Ohm] 27 + j136 8.7 + j66 9 + j63 Lantenna [nH] 52.00 12.50 11.20 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 CONTROL INTERFACE Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don't care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events: The TX register is ready to receive the next byte (RGIT) The FIFO has received the preprogrammed amount of bits (FFIT) Power-on reset (POR) FIFO overflow (FFOV) / TX register underrun (RGUR) Wake-up timer timeout (WKUP) Negative pulse on the interrupt input pin nINT (EXT) Supply voltage below the preprogrammed value is detected (LBD) FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out. Timing Specification Symbol tC H tC L tS S tS H tS H I tD S tD H tO D Parameter Clock high time Clock low time Select setup time (nSEL falling edge to SCK rising edge) Select hold time (SCK falling edge to nSEL rising edge) Select high time Data setup time (SDI transition to SCK rising edge) Data hold time (SCK rising edge to SDI transition) Data delay time Minimum value [ns] 25 25 10 10 25 5 5 10 Timing Diagram Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Control Commands Control Command 1 2 3 4 5 6 7 8 9 Configuration Setting Command Power Management Command Frequency Setting Command Data Rate Command Receiver Control Command Data Filter Command FIFO and Reset Mode Command Receiver FIFO Read Command Synchron Pattern Command Related Parameters/Functions Frequency band, crystal oscillator load capacitance, baseband filter bandwidth, etc. Receiver/Transmitter mode change, synthesizer, xtal osc, PA, wake-up timer, clock output can be enabled here Data frequency of the local oscillator/carrier signal Bit rate gain, digital RSSI threshold Data filter type, clock recovery parameters Data FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable RX FIFO can be read with this command Synchron pattern AFC parameters b7 to b0 a1 to a0, rl1 to rl0, st, fi, oe, en mp, m3 to m0, p2 to p0 ob1 to ob0, lpx, ddit, ddy, bw1 to bw0 t7 to t0 r4 to r0, m7 to m0 d6 to d0, en d2 to d0, v4 to v0 Related control bits el, ef, b1 to b0, x3 to x0 er, ebb, et, es, ex, eb, ew, dc f11 to f0 cs, r6 to r0 g1 to g0, r2 to r0 al, ml, s1 to s0, f2 to f0 f3 to f0, s1 to s0, ff, fe Function of pin 16, Valid Data Indicator, baseband bw, LNA p16, d1 to d0, i2 to i0, 10 AFC Command 11 TX Configuration Control Command Modulation parameters, output power, ea 12 PLL Setting Command 13 Transmitter Register Write Command CLK out buffer speed, low power mode of the crystal oscillator, dithering, PLL loop delay, bandwidth TX data register can be written with this command Wake-up time period Enable low duty-cycle mode. Set duty-cycle. LBD voltage and microcontroller clock division ratio Status bits can be read out 14 Wake-Up Timer Command 15 Low Duty-Cycle Command Low Battery Detector and 16 Microcontroller Clock Divider Command 17 Status Read Command In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the command registers after power-on. Description of the Control Commands 1. Configuration Setting Command bit 15 1 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 el 6 ef 5 b1 4 b0 3 x3 2 x2 1 x1 0 x0 POR 8008h Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level. Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output. b1 0 0 1 1 b0 0 1 0 1 Frequency Band [MHz] Reserved 433 868 915 x3 x2 0 0 0 0 0 0 0 0 x1 0 0 1 1 x0 0 1 0 1 Crystal Load Capacitance [pF] 8.5 9.0 9.5 10.0 ... 1 1 1 1 1 1 0 1 15.5 16.0 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 2. bit Power Management Command 15 1 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 er 6 ebb 5 et 4 es 3 ex 2 eb 1 ew 0 dc POR 8208h Bit er ebb et es ex eb ew dc Function of the control bit Enables the whole receiver chain The receiver baseband circuit can be separately switched on Switches on the PLL, the power amplifier, and starts the transmission (If TX register is enabled) Turns on the synthesizer Turns on the crystal oscillator Enables the low battery detector Enables the wake-up timer Disables the clock output (pin 8) Related blocks RF front end, baseband, synthesizer, oscillator Baseband Power amplifier, synthesizer, oscillator Synthesizer Crystal oscillator Low battery detector Wake-up timer Clock output buffer The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time. Logic connections between power control bits: Note: * If both et and er bits are set the chip goes to receive mode. * FSK / nFFSEL input are equipped with internal pull-up resistor. To achieve minimum current consumption do not pull this input to logic low in sleep mode. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 3. Frequency Setting Command bit 15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 6 f6 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 POR A680h The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of range, the previous value is kept. The synthesizer band center frequency f0 can be calculated as: f0 = 10 * C1 * (C2 + F/4000) [MHz] The constants C1 and C2 are determined by the selected band as: Band [MHz] 433 868 915 4. Data Rate Command C1 1 2 3 C2 43 43 30 bit 15 1 14 1 13 0 12 0 11 0 10 1 9 1 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C623h The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs. BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps] In the receiver set R according to the next function: R= (10000 / 29 / (1+cs*7) / BR) - 1, where BR is the expected bit rate in kbps. Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Data rate accuracy requirements: Clock recovery in slow mode: BR/BR < 1/(29*Nbit) Clock recovery in fast mode: BR/BR < 3/(29*Nbit) BR is the bit rate set in the receiver and BR is the bit rate difference between the transmitter and the receiver. Nbit is the maximum number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and to be careful to use the same division ratio in the receiver and in the transmitter. 5. Receiver Control Command Bit 15 14 13 12 1 0 0 1 11 10 9 8 7 i2 6 i1 5 i0 4 3 2 r2 1 r1 0 r0 POR 9080h 0 p16 d1 d0 g1 g0 Bit 10 (p16): pin16 function select P16 0 1 Function of pin 16 Interrupt input VDI output Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting: d1 0 0 1 1 d0 0 1 0 1 Response Fast Medium Slow Always on Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select: i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 1 i0 0 1 0 1 0 1 0 1 BW [kHz] reserved 400 340 270 200 134 67 reserved Bits 2-0 (r2 to r0): RSSI detector threshold: r2 0 0 0 Bits 4-3 (g1 to g0): LNA gain select: g1 0 0 1 1 g0 0 1 0 1 relative to maximum [dB] 0 -6 -14 -20 RSSIth = RSSIsetth + GLNA 7.Data Filter Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 0 7 al 6 ml 5 1 4 s 3 1 2 f2 1 f1 0 f0 POR C22Ch 0 1 1 1 1 r1 0 0 1 1 0 0 1 0 r0 0 1 0 1 0 1 0 1 RSSIsetth [dBm] -103 -97 -91 -85 -79 -73 Reserved Reserved The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: Bit 7 (al): Clock recovery (CR) auto lock control, if set. CR will start in fast mode, then after locking it will automatically switch to slow mode. Bit 6 (ml): Clock recovery lock control 1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended) 0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended) Using the slow mode requires more accurate bit timing (see Data Rate Command). Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Bits 4 (s): Select the type of the data filter: s 0 1 Filter Type Digital filter Analog RC filter Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate Command. Note: Bit rate can not exceed 115 kbps in this mode. Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. Bits 2-0 (f2 to f0): DQD threshold parameter. Note: To let the DQD report "good signal quality" the threshold parameter should be 4 in cases where the bit-rate is close to the deviation. At higher deviation/bit-rate settings, a higher threshold parameter can report "good signal quality" as well. The table shows the optimal filter capacitor values for different data rates 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps 256 kbps 12 nF 8.2 nF 6.8 nF 3.3 nF 1.5 nF 680 pF 270 pF 150 pF 100 pF Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used. 7. bit FIFO and Reset Mode Command 15 1 14 1 13 0 12 0 11 1 10 0 9 1 8 0 7 f3 6 f2 5 f1 4 f0 3 sp 2 al 1 ff 0 dr POR CA80h Bits 7-4 (f4 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level. Bit 3 (sp): Select the length of the synchron pattern: sp 0 1 Byte1 2Dh Not used Byte0 (POR) D4h D4h Synchron Pattern (Byte1+Byte0) 2DD4h D4h Note: Byte0 can be programmed by the Synchron Pattern Command. Bit 2 (al): Set the input of the FIFO fill start condition: al 0 1 Synchron pattern Always fill Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 500 mV glitch in the power supply may cause a system reset. Note: To restart the synchron pattern recognition, bit 1 should be cleared and set. 8. bit Synchron pattern Command 15 1 14 1 13 0 12 0 11 1 10 1 9 1 8 0 7 b7 6 b6 5 b5 4 b4 3 b3 2 b2 1 b1 0 b0 POR CED4h The Byte0 used for synchron pattern detection can be reprogrammed by B 9.Receiver FIFO Read Command bit 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POR B000h With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command. Note: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock signal is not 50 % the shorter period of the clk pulse should be at least 2/fref second. 10.AFC Command bit 15 1 14 1 13 0 12 0 11 0 10 1 9 0 8 0 7 a1 6 a0 5 rl1 4 rl0 3 st 2 fi 1 oe 0 en POR C4F7h Bit 7-6 (a1 to a0): Automatic operation mode selector: a1 0 0 1 1 rl1 0 0 1 1 a0 0 1 0 1 rl0 0 1 0 1 Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the foffset only during receiving (VDI=high) Keep the foffset value independently from the state of the VDI signal Max deviation No restriction +15 fres to -16 fres +7 fres to -8 fres +3 fres to -4 fres Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values: f res: 315, 433 MHz bands: 2.5 kHz 868 MHz band: 5 kHz 915 MHz band: 7.5 kHz Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block. Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement uncertainty is about the half. Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL. Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit. Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit changes state in every measurement cycle. In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the same result in two subsequent cycles. There are three operation modes, examples from the possible application: 1, (a1=0, a0=1) the circuit measures the frequency offset only once after power up. This way, extended TX-RX maximum distance can be achieved. Possible application: In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an interferer. 2a, (a1=1, a0=0) the circuit automatically measures the frequency offset during an initial effective low data rate pattern -easier to receive- (i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the corrected frequency settings. 2b, (a1=1, a0=0) the transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility of reducing it. In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use these settings when receiving signals from different transmitters transmitting in the same nominal frequencies. 3, (a1=1, a0=1) It's the same as 2a and 2b modes, but suggested to use when a receiver operates with Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 only one transmitter. After a complete measuring cycle, the measured value is kept independently of the state of the VDI signal. 11. bit TX Configuration Control Command 15 1 14 0 13 0 12 1 11 1 10 0 9 0 8 mp 7 m3 6 m2 5 m1 4 m0 3 0 2 p2 1 p1 0 p0 POR 9800h Bits 8-4 (mp, m3 to m0):FSK modulation parameters: The resulting output frequency can be calculated as: fout = f0 + (-1)SIGN * (M + 1) * (15 kHz) Where: f0 is the channel center frequency (see the Frequency Setting Command) M is the four bit binary number The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance. 12. bit PLL Setting Command 15 1 14 1 13 0 12 0 11 1 10 1 9 0 8 0 7 0 6 ob1 5 ob0 4 1 3 ddy 2 ddit 1 1 0 bw0 POR CC77h/CC67 Note1: POR default setting of the register carefully selected to cover almost all typical applications. Bit 6-5 (ob1-ob0): Microcontroller output clock buffer rise and fall time control Note2: For A0 version, the default value is CC67, it is necessary to use CC77 instead of CC67 in the application program., Note3: For A1 version, you can use the default value CC77. ob1 0 0 1 ob0 0 1 X Selected uC CLK frequency 5 or 10 MHz (recommended) 3.3 MHz 2.5 MHz or less Note: Needed for optimization of the RF performace. Optimal settings can vary by the actual external parasitic capacitances. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Bit 3 (ddy): Switches on the delay in the phase detector when this bit is set. Bit 2 (ddit): When set, disables the dithering in the PLL loop. Bit 1-0 (bw1-bw0): PLL bandwidth can be set for optimal TX RF performance. bw0 0 1 Max bit rate [kbps] 86.2 256 Phase noise at 1MHz offset [dBc/Hz] -107 -102 13. bit Transmitter Register Write Command 15 1 14 0 13 1 12 1 11 1 10 0 9 0 8 0 7 t7 6 t6 5 t5 4 t4 3 t3 2 t2 1 t1 0 t0 POR B8AAh With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting Command. Multiple byte write with Transmit Register Write Command: Note: Alternately the transmit register can be directly accessed by nFFSEL (pin6). 14. bit Wake-Up Timer Command 15 1 14 1 13 1 12 r4 11 r3 10 r2 9 r1 8 r0 7 m7 6 m6 5 m5 4 m4 3 m3 2 m2 1 m1 0 m0 POR E196h The wake-up time period can be calculated by (m7 to m0) and (r4 to r0): Twake-up = M * 2R [ms] Note: * For continual operation the et bit should be cleared and set at the end of every cycle. * For future compatibility, use R in a range of 0 and 29. 15. bit Low Duty-Cycle Command 15 1 14 1 13 0 12 0 11 1 10 0 9 0 8 r0 7 d6 6 d5 5 d4 4 d3 3 d2 2 d1 1 d0 0 en POR C80Eh With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode. The time cycle is determined by the Wake-Up Timer Command. The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.) Duty-Cycle= (D * 2 +1) / M *100% Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command. Application proposal for LPDM(Low Power Duty-cycle Mode) Receivers: Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode. Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command. 16. bit Low Battery Detector and Microcontroller Clock Divider Command 15 1 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 d2 6 d1 5 d0 4 0 3 v3 2 v2 1 v1 0 v0 POR C000h The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage Vlb of the detector: Vlb= 2.2 + V * 0.1 [V] Clock divider configuration: d2 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 Clock Output Frequency [ MHz] 1 1.25 1.66 2 2.5 3.33 5 10 The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command. 17. Status Read Command The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits will be clocked out on the SDO pin as follows: Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Status Register Read Sequence with FIFO Read Example: RGIT FFIT POR RGUR FFOV WKUP EXT LBD FFEM ATS RSSI DQD CRL ATGL OFFS(6) OFFS(3) -OFFS(0) TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command) The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the FIFO read methods) Power-on reset (Cleared after Status Read Command) TX register under run, register over write (Cleared after Status Read Command) RX FIFO overflow (Cleared after Status Read Command) Wake-up timer overflow (Cleared after Status Read Command) Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command) Low battery detect, the power supply voltage is below the pre-programmed limit FIFO is empty Antenna tuning circuit detected strong enough RF signal The strength of the incoming signal is above the pre-programmed limit Data quality detector output Clock recovery locked Toggling in each AFC cycle MSB of the measured frequency offset (sign of the offset value) Offset value to be added to the value of the frequency control parameter (Four LSB bits) Note: In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0). TX REGISTER BUFFERED DATA TRANSMISSION In this operating mode (enabled by bit el, in the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send out the data from the first register Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 (with the given bit rate) when bit et is set with the Power Management Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller. TX register simplified block diagram (before transmit) TX register simplified block diagram (during transmit) Typical TX register usage Note: The content of the data registers are initialized by clearing bit et. RX FIFO BUFFERED DATA READ In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller. Interrupt Controlled Mode: The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. FIFO Read Example with FFIT Polling Note: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock signal is not 50% the shorter period of the clk pulse should be at least 2/fref second. Polling Mode: When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available to read out the content of the FIFO. RECOMMENDED PACKET STRUCTURES Preamble Synchron word (Can be network ID) Minimum length 4 - 8 bit (1010b or 0101b) D4h (programmable) ? 4 bit - 1 byte Payload CRC Recommended length 8 -12 bit (e.g. AAh or 55h) 2DD4h (D4 is programmable) ? 2 byte CRYSTAL SELECTION GUIDELINES The crystal oscillator of the RF12B requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 capacitance value is programmable from 8.5 pF to 16 pF in 0.5pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore fLO is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error. Whenever a low frequency error is essential for the application, it is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the "midrange", for example 16 pF. The "pull-ability" of the crystal is defined by its motional capacitance and C0. Maximum XTAL Tolerances Including Temperature and Aging [ppm] Bit Rate: 2.4 kbps 315 MHz 433 MHz 868 MHz 915 MHz 9.6 kbps 315 433 868 915 MHz MHz MHz MHz 30 20 15 8 8 45 50 30 15 15 30 25 20 10 10 45 50 30 20 15 Deviation [+/- kHz] 60 75 50 25 25 Deviation [+/- kHz] 60 70 50 25 25 75 75 70 30 30 90 100 80 40 40 105 100 100 50 50 120 100 100 60 50 75 100 70 30 30 90 105 120 100 100 100 90 40 40 100 100 50 50 60 50 Bit Rate: Bit Rate: 38.4 kbps 315 MHz 433 MHz 868 MHz 915 MHz 30 don't use don't use don't use don't use Deviation [+/- kHz] 45 60 7 30 5 3 3 20 10 10 75 50 30 20 15 90 105 75 100 50 75 25 30 25 30 120 100 75 40 40 Bit Rate: 115.2 kbps 315 MHz 433 MHz 868 MHz 915 MHz 105 don't use don't use don't use don't use 120 4 3 don't use don't use Deviation [+/- kHz] 135 30 20 10 10 150 50 30 20 15 165 180 195 70 100 100 50 25 25 70 35 30 80 45 40 RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 crystal placement on the RX and TX PCBs. To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies. It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0). TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and Blocking: Note: * LNA gain maximum, filter bandwidth 67 kHz, data rate to 9.6 kbps, AFC switched off, FSK deviation +/- 45 kHz, Vdd = 2.7 V * Measured according to the descriptions in the ETSI Standard EN 300 220-1 v2.1.1 (2006-01 Final Draft), section 9 * The ETSI limit in the figure is drawn by taking 109dBm typical sensitivity into account Phase Noise Performance in the 915 MHz (Green) 868 MHz (Red) and 433 MHz (Blue) Bands: Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 (Measured under typical conditions: Top = 27 oC; Vdd = Voc = 2.7 V) BER Curves in 433 MHz Band: BER Curves in 868 MHz Band: Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 The table shows the optimal receiver baseband bandwidth (BW) and transmitter deviation frequency ( fFSK) selection for different data rates. 1.2 kbps BW=67 kHz 2.4 kbps BW=67 kHz 4.8 kbps BW=67 kHz 9.6 kbps BW=67 kHz 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps BW=67 kHz BW=134 kHz BW=134 kHz BW=200 kHz fFSK =45 kHz fFSK =45 kHz fFSK =45kHz fFSK =45 kHz fFSK =45 kHz fFSK =90 kHz fFSK =90 kHz fFSK =120 kHz Receiver Sensitivity over Ambient Temperature (433 MHz, 9.6 kbps, fFSK: 45 kHz, BW: 67 kHz): Receiver Sensitivity over Ambient Temperature Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 (868 MHz, 9.6 kbps, fFSK: 45 kHz, BW: 67 kHz): Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 REFERENCE DESIGNS Schematic PCB layout Top view Bottom view Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 SGS Reports Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 RF12B BONDING DIAGRAM Pad Opening: 85um square, except 76um octagon pads (AN1, AN2) Die Size: 2750 X 3315 um Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RF12B V1.1 This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express HOPE MICROELECTRONICS CO.,LTD Add:4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: Fax: Email: 86-755-86096602 86-755-86096587 sales@hoperf.com http://www.hoperf.cn http://hoperf.en.alibaba.com (c)2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. Website: http://www.hoperf.com Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com |
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